1. Field of the Invention
The present invention relates in general to semiconductor integrated circuits, and more particularly to the reduction of parasitic transistor current in complementary metal-oxide-semiconductor (CMOS) integrated circuits.
2. Description of the Related Art
It is well known that the doped semiconductor layers of CMOS integrated circuits form parasitic bipolar transistors that conduct unwanted current under certain conditions. FIG. 1 shows an example, discussed in U.S. Pat. No. 5,338,986 to Kurimoto (and the corresponding Japanese Patent Application Publication No. 5-335500), of an inverting output circuit formed on a P-type semiconductor substrate 601 with an N-type well 602. A P-type source region 603, a P-type drain region 604, and a gate electrode 605 at the surface of the N-type well 602 constitute a P-channel metal-oxide-semiconductor field-effect transistor (PMOS transistor) 606. Also disposed at the surface of the N-type well 602 is an N-doped region 607 with a high impurity concentration. An N-type source region 608, an N-type drain region 609, and a gate electrode 610 at the surface of the P-type substrate 601 constitute an N-channel metal-oxide-semiconductor field-effect transistor (NMOS transistor) 611. A P-doped region 612 with a high impurity concentration is also formed in the surface of the substrate 601.
The P-type source region 603 is biased to a first power supply potential VCC of, for example three volts (3 V). The N-type well 602 is biased through the N-type highly doped region 607 to a second power supply potential VDD of, for example, 15 V. The N-type source region 608 is biased to a third power supply potential VSS of, for example, zero volts (0 V). The P-type substrate 601 is biased through the P-type highly doped region 612 to a fourth power supply potential VEE of, for example, −15 V. VCC and VSS are supplied from an external source; VDD and VEE are generated from VCC and VSS by a potential converter (not shown) in the integrated circuit chip.
This circuit includes two parasitic bipolar transistors Q1, Q2. Transistor Q1 has a PNP structure formed by the P-type source region 603, the N-type well 602, and the P-type substrate 601; transistor Q2 has an NPN structure formed by N-type source region 608, the P-type substrate 601, and the N-type well 602. Parasitic resistors R1 to R4 are also present. R1, determined by the distance between regions 603 and 607, is the base resistance of transistor Q1; R2, determined by the distance between regions 607 and 608, is the collector resistance of transistor Q2; R3, determined by the distance between regions 603 and 612, is the collector resistance of transistor Q1; R4, determined by the distance between regions 608 and 612, is the base resistance of transistor Q2. These parasitic transistors and resistors, shown schematically in FIG. 2, are equivalent to a thyristor, as discussed in Japanese Patent Application Publication No. 9-8147.
Normally VDD exceeds VCC and VSS exceeds VEE (VDD>VCC>VSS>VEE), so PNP transistor Q1 has a base potential (VDD) higher than its emitter potential_(VCC) and NPN transistor Q2 has a base potential (VEE) lower than its emitter potential (VSS). Both parasitic transistors Q1, Q2 are accordingly switched off and do not affect circuit operation.
Since VDD and VEE are generated from VCC and VSS, however, at power-up VCC and VSS reach their normal levels before VDD and VEE. There is therefore an interval during which VCC and VSS are stable while VDD and VEE are still rising and falling. During this interval, VCC may exceed VDD (VCC>VDD) and VEE may exceed VSS (VSS<VEE), allowing the parasitic transistors Q1, Q2 to turn on and leading to the unwanted flow of currents I1, I2 from VCC to VSS as indicated in FIG. 2.
These currents I1, I2 have various adverse effects on the operation of the integrated circuit. For example, they can cause excessive standby current dissipation. They may also overload the potential converter and prevent it from generating the necessary VDD and VEE potentials. In the worst case, the integrated circuit chip as a whole is so overloaded by parasitic currents that it is destroyed.